The present invention relates to a semiconductor memory device and more particularly to a semiconductor multilevel memory device which allows the information to be accumulated per unit of the memory on an extremely high storage level even in the case of the low power voltage and the power consumption to be small.
The semiconductor memory which can be represented by the dynamic random access memory (hereinafter abbreviated as DRAM) has been developed year by year with the ever increasing integrated degree and a memory device per unit of the semiconductor memory (hereinafter abbreviated as the memory cell) and a peripheral circuit have been made increasingly fine. However, such improvement of the integration through refinement must be accompanied by the great advance of the element processing techniques such as lithography or etching and as usual a certain amount of time is required for the development of such techniques.
Meanwhile, the demand for the large capacity semiconductor memory has been ever increasing and in the new field of the small size computer for use in the offices and its terminal which are recently making a remarkable progress, the large capacity and the low power consumption semiconductor has been sincerely cried for. In other words, according to the prior semiconductor memory, it has been said that not only the degree of the integration but also other performances such as the power consumption leave much to be desired.
To meet the above-mentioned demands, of the processing techniques popular at the present time, the memory having multiple level storage structure (MLS memory) is considered to be effective for achieving the more highly integrated semiconductor memory. This is intended for increasing the integration of the memory cell substantially by making a single memory cell store the information comprising three values.
As the MLS memory which has been conventionally known, there is a charge transfer device (hereinafter abbreviated as the CTD). This device is described in detail in, for example, L. Terman et al. IEEE Journal of Solid-State Circuits. Vol. sc-16, No. 5, pp. 472-478, October 1981, M. Yamada et al. Proceedings of the 9th Conference on Solid-State Devices, Tokyo 1977, pp. 263-268, issued on January 1978.
However, up to the present, the MLS memory in which the CTD is used has not yet been put into practical use much. For, to prevent the multilevel data which is intrinsically the analogue signal from being attenuated due to the limited transfer efficiency peculiar to the CTD, the multiple values cannot be increased too much. Or since the driving pulse voltage is necessary to be raised to raise the transfer efficiency, the power consumption is likely to become extremely great apart from it being intrinsically a high capacity loaded device. Furthermore, the high accuracy A/D to D/A converters are necessary for the loop of each CTD, even if the memory cell can be made smaller, the degree of the integration cannot be increased due to the constraint caused by the peripheral circuit.
In view of the above-described disadvantages peculiar to the MLS memory in which CTD is used, the present invention conceived making the dynamic memory (DRAM) in which the addressing is conducted by both rows and columns store multiple values and providing the A/D to D/A converters with the sensing and writing system. If the XY addressing is used, the transfer efficiency need not be taken into consideration and the number of gates which are to be driven is made smaller, reducing the power consumption. However, in order to design the DRAM in the form of the MLS memory, it is necessary to solve the following extremely difficult problems. First, even if the memory cell has stored the multilevel information (analogue signal) having the dynamic range (which is divided into the multilevel information) ranging up to the maximum 5 V.sub.pp, for example, since the capacity of the parasitic data line is often larger by one position or thereabove than the capacity of the memory cell, the dynamic range below the maximum 500 m V.sub.pp, for example, results when that data is read out onto the data line. It is extremely difficult to load a multiplicity of A/D converters on the chip for accurately amplifying such small analogue signal and converting it into the digital value, except for the case where the number of levels of the multiple values is small. In particular, it is extremely difficult to provide A/D converters to each data line, unless the pitch of the data line is large.
In this case, note that the MLS memory exhibits an excellent performance as the large capacity memory only when memory cells equal to or above the ordinary memory storing the binary number are provided on the chip of an equal or larger size. Namely, if the amount of charges of the signal of the single memory cell in the current DRAM is Qs', if the manufacturing processing technique is the same, the amount of charges of the signal which is allowed to the single level of the MLS memory having the N-multiple value, approximately becomes Q'N, which is the extremely stringent condition. Accordingly, XY addressing type MLS memory simultaneously needs an amplifier which allows the minute signal to be accurately amplified and an A/D converter which is compact and has a high accuracy. The lack of such possibility of obtaining those devices has left the MLS memory of this sort aside.
The invention has achieved the novel XY addressing type MLS memory, as described in the European patent application Publication No. 130614, 139196 and 148488, and achieved a large capacity semiconductor memory in which the power consumption is small.
The above-described memory having the multiple level storage structure (MLS memory) has a novel minute voltage amplifier which is suited to the large capacity memory and A/D to D/A converters which are extremely simple and low in the power consumption and yet highly accurate, having the peripheral circuit having the low power consumption. Thanks thereto, it has become possible to replace the magnetic disc unit which requires the large volume and the large power consumption by the semiconductor memory in the small size computer system.